The move toward faster operating speeds and higher transistor packing densities in the semiconductor chip industry has prompted the introduction of new materials, such as low-k dielectrics. As the minimum feature size on integrated circuits shrinks below 0.18 μm, the wiring between transistors is not only more closely packed, but the wires may also function as the plates of a capacitor making them more prone to crosstalk. The crosstalk problem may be reduced by using lower resistance metal (such as copper) for interconnect, and lower permittivity dielectric material for isolation, such as dielectric materials with a relative permittivity k<3.
A problem with low permittivity or low-k dielectrics results from the desire to reduce the relative permittivity k to as low a value as possible while still maintaining the characteristics of a good insulator. Also, unlike dielectrics such as silicon dioxide, which are comparatively hard and inert, low-k dielectrics are more difficult to handle during semiconductor processing because they are typically much softer, more porous, and more prone to chemical reactions during high temperature processes needed for chip making.
Furthermore, etching trenches or vias in low-k dielectrics can be a challenge due to the more complicated chemical composition of the dielectric material. For example, etching low-k dielectrics using conventional dielectric etching processes often produces non-volatile etch products. The non-volatile etch products tend to deposit on the surfaces of etched features, causing problems such as striation, slow etch rate, or even etch stop. Since a low-k dielectric etching process is typically carried out in a vacuum chamber, frequent chamber cleaning is also required to remove the deposited non-volatile etch products from the surfaces inside the vacuum chamber. Chamber cleaning consumes time and resources, and can slow down the throughput in device fabrication.
Oxygen can be used to remove the etch products from feature surfaces and possibly other surfaces inside the etching chamber. But, since low-k dielectrics are typically etched using a photoresist mask, the added oxygen also attacks the photoresist, causing faster mask erosion. As the feature sizes shrink, the photoresist mask gets thinner, and the ratio of the rate of etching the low-k dielectric layer to the rate of mask erosion becomes a major concern in low-k dielectric etching processes.
The ratio of the rate of etching the low-k dielectric layer to the rate of etching one of the adjacent layers of other materials is called etching selectivity. In addition to the etching selectivity with respect to the overlying mask layer, etching selectivity with respect to an underlying material is also critical for a low-k dielectric etching process. For example, a liner/barrier layer has been used between a conductive material such as the copper lines and a low-k dielectric material to prevent by-products, such as moisture produced during the formation of the low-k dielectric, from diffusing onto the conductive material. Such a liner/barrier layer needs to have a low dielectric constant in order to maintain the low-k characteristic of the dielectric-barrier/liner stack between metal lines. The low-k barrier/liner layer also acts as an etch-stop layer for the low-k dielectric etching process, so that the underlying metal will not be exposed to the etching environment. Therefore, the low-k dielectric etching process should also be highly selective with respect to the low-k barrier/liner layer.